The present invention relates to memory testing method and apparatus. More specifically, the present invention relates to a method of quickly testing computer memory, and computer memory having a fault analyzer.
DRAM (Dynamic Random Access Memory) testing times are very long compared to ASIC (Application Specific Integrated Circuits or standard logic) testing times. Typically DRAM testing takes one to two minutes compared to two to ten seconds for standard logic, depending on organization and complexity. This is because, for the most part, DRAM pin counts are typically much lower than ASIC pin counts. For example, a 64 Meg DRAM organized as xc3x978 has 32 pins compared to typically more than 200 pins for ASICs. Lower DRAM pin count constrains data throughput and increase testing times since it takes longer to load and verify test patterns. Further, test failures are downloaded to an external, slower hardware or software program where they are analyzed off-line to determine DRAM repairability.
Memory such as DRAM stores bits organized in a grid of rows and columns where each bit is a binary digit. To increase yield of usable chips, DRAMs are typically manufactured containing a number of redundant, or spare, rows, redundant columns, or both. When a faulty bit is found, the row or the column containing the faulty bit is replaced by one of the redundant rows or redundant columns. A DRAM is repairable when the number of redundant rows is greater than or equal to the number of rows requiring replacement by a redundant row and the number of redundant columns is greater than or equal to the number of columns requiring replacement by a redundant column. If this condition is not met, then the DRAM is not repairable. Determining repairability depends on determining defect clustering from the raw data stream of addresses (column and row) and failed data bits in each word. If a DRAM can be repaired, the DRAM is then repaired through laser zapping to activate good columns or rows and retested to determine usability. The process of determining repairability, offline repair, and retesting requires additional testing time.
When memory is embedded inside an ASIC, testing and repairing the memory is even more difficult and costly. This is due to longer test times, extra hardware, and additional handling steps to analyze and determine the memory""s repairability. An ASIC tester is required to handle the complexities associated with ASICs (greater number of signals, higher signal frequencies or varying signal interfaces). Unlike DRAM testers, ASIC testers typically handle one part at a time, usually due to the higher pin counts (higher than 200, typically). Suppliers rely on the greater number of signal pins and higher frequencies, even BIST (built-in self test), to speed up logic and embedded memory testing. But as DRAM exceed one Megabits and beyond, an ASIC tester will exceed practical limits due to longer test patterns or wider words, or both. A similar repairability analysis to that done in DRAM testers must also be performed external to the ASIC tester. Also, ASIC testers and BIST focus on detecting failures not determining repairability. ASIC testers could keep track of fault locations but at the cost of additional external hardware and software with longer test times.
The DRAM testing times may be reduced through BIST techniques and by using wide words (wider data throughput), but the reduction is not significant, especially for large DRAMs of one Megabit or more. Similar problems exist for other types of memory modules such as Flash, EEPROM (electrically erasable programmable read-only memory), large SDRAM (Synchronous DRAM), and others where long testing times and determining repairability are required.
Other techniques have been used to reduce DRAM testing times. For example, external, highly specialized DRAM testers have been used to test between 16 to 64 devices at a time to compensate for the lower data throughput. In essence, testing multiple memory devices at the same time reduces per-chip testing time to about two to four seconds. However, this approach does not reduce the testing time for each DRAM.
Accordingly, there is a need for a method and apparatus for faster memory fault analysis.
These needs are met by the present invention. According to one aspect of the present invention, a storage apparatus includes memory having addressable storage locations and fault analyzer for storing address of a fault location within the memory. Because the fault analyzer is within the storage apparatus, the memory can be tested quickly.
According to another aspect of the present invention, a technique of testing a memory device having addressable location is disclosed. First, expected data and actual data are compared. Then, when the expected data is not equal to the actual data, the address of memory location is stored within the memory device.